Ultra Start 16xx Manual de usuario descargar pdf (Pagina 4)

MEB/0404

• No accumulator

bottleneck

• Single-cycle operations

• Silicon area 30% smaller

than ‘8051 lowers cost

• Industries most efficient

C-code density

Write Less Code, Use

Fewer Cycles

Modern 16-bit RISC CPU

16-bit ALU

R10

R11

R12

R13

R14

R15

R3/CG

R2/SR

R1/SP

R0/PC

16-bit ALU

R10

R11

R12

R13

R14

R15

R3/CG

R2/SR

R1/SP

R0/PC

Modern 16-bit RISC CPU is optimized for modern programming techniques.

•The MSP430’s architecture provides the flexibility of 16 fully addressable, single-cycle 16-bit

CPU registers. The large CPU register file eliminates what is typically a single working file or

accumulator bottleneck. The CPU registers are fully accessible including the program counter,

stack pointer, status register and 12 working registers.

•The CPU also integrates a constant generator to automatically generate the six most used

immediate values. The constant generator has the effect of reducing code size by generator this

common constants (or literals) using hardware, eliminating what would be immediate values

embedded in code.

•The modern Reduced Instruction Set (RISC) design of the CPU offers versatility through

simplicity using only 27 easy-to-understand instructions and seven consistent addressing

modes. All memory spaces – Flash, RAM, peripherals and CPU registers - use the exact same

instructions and addressing modes. All instructions can also be used in a byte format as well.

The MSP430 is an orthogonal design because all instructions are used consistently though all

areas of the device.

•Up to 8 MIPS of performance is available today, with more planned.

•The result is a 16-bit, ultra-low power CPU that has more effective processing throughput, is

smaller in size, and more code-efficient than other 8/16-bit microcontrollers. When using the

MSP430, this results in programmers writing less lines of code. Now it’s possible to develop

ultra-low power, high-performance applications at a fraction of the code size previously

possible.

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